Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing
Academic Article
Publication Date:
2017
Short description:
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing / Sau, C., Palumbo, F., Pelcat, M., Heulot, J., Nogues, E., Menard, D., Meloni, P., Raffo, L.. - In: IEEE EMBEDDED SYSTEMS LETTERS. - ISSN 1943-0663. - 9:3(2017), pp. 65-68. [10.1109/LES.2017.2703585]
abstract:
Applicable in different fields and markets, low energy high efficiency video coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this letter, a field programmable gate array implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in conjunction with hardware reconfiguration, guarantees a tunable interpolation system offering an energy versus quality tradeoff to further reduce energy.
Iris type:
1.1 Articolo in rivista
Keywords:
Embedded applications; field programmable gate array (FPGA); FIR filters; low power architectures; low power design; reconfigurable computing; runtime reconfiguration; signal processing; Control and Systems Engineering; Computer Science (all)
List of contributors:
Sau, Carlo; Palumbo, Francesca; Pelcat, Maxime; Heulot, Julien; Nogues, Erwan; Menard, Daniel; Meloni, Paolo; Raffo, Luigi
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